By Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
This booklet constitutes the refereed lawsuits of the eleventh foreign Symposium on utilized Reconfigurable Computing, ARC 2015, held in Bochum, Germany, in April 2015.
The 23 complete papers and 20 brief papers offered during this quantity have been conscientiously reviewed and chosen from eighty five submissions. they're prepared in topical headings named: structure and modeling; instruments and compilers; platforms and purposes; network-on-a-chip; cryptography purposes; prolonged abstracts of posters. additionally, the publication comprises invited papers on funded R&D - operating and accomplished initiatives and Horizon 2020 funded projects.
Read or Download Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings PDF
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Additional resources for Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
Thus, this paper has three contributions: 1. We enhance the design framework in  to support hierarchical power-gating. Section 3 presents our compiler-assisted framework for automatically generating hierarchical power-gating decisions. Hierarchical Dynamic Power-Gating in FPGAs 29 2. We study the impact of reducing the power-gating granularity to consider power-gating sub-accelerators as well as accelerators. Section 4 quantiﬁes the impact of hierarchical power-gating. 3. We investigate whether the compiler-assisted power-gating approach used in  is suﬃcient as the granularity of power-gating decreases.
This approach is similar to  and serves as the reference. e. each hierarchical accelerators can be switched independently. In this policy, the parent accelerator remains active and does not sleep after initiating the sub-accelerator. The sub-accelerator is power-gated, however, if only the parent is required to be active. Parent is Power-Gated while Child Runs; Policy-P3: This approach also represents intra-accelerator power-gating. In this approach, we powergate the parent accelerator after it is has started a sub-accelerator.
This increases the beneﬁt from cold miss avoidance, until there are no cache misses left and the beneﬁt levels oﬀ. Since larger sparse matrices exhibit more cold misses due to large y size, the greatest beneﬁt is observed for the large matrices 1, 2 and 4, with up to 40% improvement. For matrix 5, the number of capacity misses with small caches is very large and very little beneﬁt is observed until a cache size of 16K elements. 26 5 Y. Umuroglu and M. Jahre Conclusion and Future Work We have studied how matrix structure relates to cache misses, and proposed a scheme that uses preprocessing to enhance the operation of a traditional hardware cache for FPGA SpMV accelerators.