By Juan J. Becerra, Eby G. Friedman
Analog layout matters in electronic VLSI Circuits and Systems brings jointly in a single position very important contributions and updated study leads to this fast-paced sector.
Analog layout matters in electronic VLSI Circuits and Systems serves as a great reference, delivering perception into probably the most difficult study concerns within the field.
Read or Download Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) PDF
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Additional info for Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997)
Non-step inputs, such as a ramp input , have been considered when evaluating the delay characteristics of URC lines, but have not until now been considered in RC trees . In this paper, an equation has been derived for the approximating function used in the R C tree analysis on the assumption of a ramp input, and upper and lower bounds corresponding to the same input waveform are presented. The ability to deal with ramp input signals of varying slope is viewed as a more realistic approach to practical problems of interest rather than limiting consideration to a step function excitation.
1 3) The resistive power dissipated for different RC loads calculated from (13) is shown in Table III. The load resistance R and capacitance C are listed in the first two columns, respectively. The power dissipated by the interconnect resistance determined from (13) and from SPICE are shown in the third and fourth columns, respectively. The per cent error of the analytic expression as compared to SPICE is shown in the final column. Note that the per cent error is less than 15% and typically less than 6%.
In contrast, the short-circuit power dissipation changes with both input waveform shape and output load resistance and capacitance. The ratio of the short-circuit power to the total transient power (the sum of the dynamic and short-circuit power) of a CMOS inverter with respect to the load resistance R for a given load capacitance C is shown in Figure 6. Note that with increasing load resistance, the short-circuit power dissipation cannot be neglected, since, as shown in Figure 6, it can comprise more than 20% of the total transient power dissipation.